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ZL38002 Datasheet(PDF) 21 Page - Zarlink Semiconductor Inc |
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ZL38002 Datasheet(HTML) 21 Page - Zarlink Semiconductor Inc |
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21 / 47 page  ZL38002 Data Sheet 21 Zarlink Semiconductor Inc. 3AH Read 0 00H Receive (Rout) Peak Detect Register 1 (RPDR1) Receive (Rout) Peak Detect Register 2 (RPDR2) 3BH Read 0 00H 3CH Read 0 00H Adaptation Speed Register 1 (ASR1) Adaptation Speed Register 2 (ASR2) 3DH Read 0 10H 3FH R/W 0/1/2/3 08H BRC Bootload RAM Control Register (BRCR) 1AH Read 1 00H Noise Level R Path Register 1 (NLRPR1) Noise Level R Path Register 2 (NLRPR2) 1BH Read 1 00H 3AH Read 1 00H Noise Level S Path Register 1 (NLSPR1) Noise Level S Path Register 2 (NLSPR2) 3BH Read 1 00H 1CH R/W 200H AGC Gain Register 1 (AGCGR1) AGC Gain Register 2 (AGCGR2) 1DH R/W 208H 15H R/W 320H Noise Threshold for Noise Reduction Register (NRTH) 17H R/W 320H Minimum Noise Reduction Level Register(Beta) Address CPU Access Page Reset Value Description Table 6 - Address Map (continued) |
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