ASIX ELECTRONICS CORPORATION

29

AX88178 L

USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller

7.3.4 RGMII Timing

Ttclk

Ttch

Ttcl

TXC

TXD [3:0]

TX_EN (TX_CTL)

TXC

TXD [3:0], TX_EN (TX_CTL)

Trclk

Trch

Trcl

RX_CLK (RXC)

RXD [3:0]

RX_DV (RX_CTL)

Symbol

Description

Min

Typ

Max

Units

Ttclk

TXC clock cycle time at 1000Mbps *1

7.2

8.0

8.8

ns

Ttch

TXC clock high time at 1000Mbps *2

-

4.0

-

ns

Ttcl

TXC clock low time at 1000Mbps *2

-

4.0

-

ns

-500

-

500

ps

Trclk

RX_CLK (RXC) clock cycle ime at 1000Mbps *1

7.2

8.0

8.8

ns

Trch

RX_CLK (RXC) clock high time at 1000Mbps *2

-

4.0

-

ns

Trcl

RX_CLK (RXC) clock low time at 1000Mbps *2

-

4.0

-

ns

Trsu

RXD [3:0] and RX_DV (RX_CTL) to RX_CLK (RXC) clock setup time

1.0

-

-

ns

Trhd

RXD [3:0] and RX_DV (RX_CTL) to RX_CLK (RXC) clock hold time

1.0

-

-

ns

*1: For 10Mbps and 100Mbps, Ttclk and Trclk shall scale to 400ns+/-40ns and 40ns+/-4ns respectively.

*2: For 10Mbps and 100Mbps, the typical value of Ttch, Ttcl, Trch, and Trcl shall scale to 200ns and 20ns respectively.

Trsu

Trhd

Trsu

Trhd

RXD [3:0]

RXD [7:4]

RX_DV

RX_ER

TXD [3:0]

TXD [7:4]

TX_EN

TX_ER

< 500ps

< 500ps

< 500ps

< 500ps