DSP56857 datasheet(384/662 Pages) FREESCALE

384 / 662 page

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5685X Digital Signal Controller User Manual, Rev. 4

13-18

Freescale Semiconductor

Figure 13-10. TMR Hold Register (HOLD)

See Programmer’s Sheet on Appendix page B - 88

13.9.8 Timer Channel Counter Register (CNTR)

There are four read/write Timer Channel Counter Registers in this occurrence. Their addresses

are:

TMRA0_CNTR (Timer A, Channel 0 Counter)—Address: TMRA_BASE + $5

TMRA1_CNTR (Timer A, Channel 1 Counter)—Address: TMRA_BASE + $D

TMRA2_CNTR (Timer A, Channel 2 Counter)—Address: TMRA_BASE + $15

TMRA3_CNTR (Timer A, Channel 3 Counter)—Address: TMRA_BASE + $1D

Figure 13-11. TMR Counter Register (CNTR)

See Programmer’s Sheet on Appendix page B - 89

13.10 Resets

The TMR module can only be reset by the RST signal. This forces all registers to their reset state

and clears the OFLAG signal if it is asserted. The counter will be turned off until the settings in

the Control register are changed.

13.11 Interrupts

The TMR module can generate 12 interrupts, three for each of the four counters/channels.

13.11.1 Timer Compare Interrupts

These interrupts are generated when a successful compare occurs between a counter and it’s

compare registers while the Timer Compare Flag Interrupt Enable (TCFIE) is set in the

TMR_SCR. These interrupts are cleared by writing 0 to the TCF bit in the appropriate

TMR_SCR.

Base + $4, $C,

$14, $1C

Read

HOLD VALUE

Write

Reset

000

0000

000

Base + $5. $D,

$15, $1D

Read

COUNTER

Write

Reset

000

0000

000

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