DSP56857 datasheet(383/662 Pages) FREESCALE

383 / 662 page

Quad Timer (TMR), Rev. 4

Freescale Semiconductor

13-17

13.9.5 Timer Channel Capture Register (CAP)

These read/write registers store the values captured from the counters. There are four Timer

Channel Hold Registers in this occurrence. Their addresses are:

TMRA0_CAP (Timer A, Channel 0 Capture)—Address: TMRA_BASE + $2

TMRA1_CAP (Timer A, Channel 1 Capture)—Address: TMRA_BASE + $A

TMRA2_CAP (Timer A, Channel 2 Capture)—Address: TMRA_BASE + $12

TMRA3_CAP (Timer A, Channel 3 Capture)—Address: TMRA_BASE + $1A

Figure 13-8. TMR Capture Register (CAP)

See Programmer’s Sheet on Appendix page B - 86

13.9.6 Timer Channel Load Register (LOAD)

These read/write registers store the value used to load the counter. There are four Timer Channel

Load Registers in this occurrence. Their addresses are:

TMRA0_LOAD (Timer A, Channel 0 Load)—Address: TMRA_BASE + $3

TMRA1_LOAD (Timer A, Channel 1 Load)—Address: TMRA_BASE + $B

TMRA2_LOAD (Timer A, Channel 2 Load)—Address: TMRA_BASE + $13

TMRA3_LOAD (Timer A, Channel 3 Load)—Address: TMRA_BASE + $1B

Figure 13-9. TMR Load Register (LOAD)

See Programmer’s Sheet on Appendix page B - 87

13.9.7 Timer Channel Hold Register (HOLD)

These read/write registers store the channel’s value whenever any counter is read. There are four

Timer Channel Hold Registers in this occurrence. Their addresses are:

TMRA0_HOLD (Timer A, Channel 0 Load)—Address: TMRA_BASE + $4

TMRA1_HOLD (Timer A, Channel 1 Load)—Address: TMRA_BASE + $C

TMRA2_HOLD (Timer A, Channel 2 Load)—Address: TMRA_BASE + $14

TMRA3_HOLD (Timer A, Channel 3 Load)—Address: TMRA_BASE + $1C

Base + $2, $A,

$12, $1A

Read

CAPTURE VALUE

Write

Reset

000

0000

000

0000

Base + $3, $B,

$13, $1B

Read

LOAD VALUE

Write

Reset

000

0000

000

0000

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