DSP56857 datasheet(379/662 Pages) FREESCALE

379 / 662 page

Quad Timer (TMR), Rev. 4

Freescale Semiconductor

13-13

13.9.1.5 Count Length (LENGTH)—Bit 5

This bit determines whether the counter counts to the compare value and then reinitializes itself,

or the counter continues counting past the compare value (binary roll-over).

•

0 = Roll-over

•

1 = Count till compare, then reinstalled. If counting up, successful compare occurs when

counter reaches CMP1 value. If counting down, successful compare occurs when counter

reaches CMP2 value.

13.9.1.6 Count Direction (DIR)—Bit 4

This bit selects either the normal count-up direction, or the reverse down direction.

•

0 = Count Up

•

1 = Count Down

13.9.1.7 External Initialization (EXT INIT)—Bit 3

This bit enables another counter/timer within the same module to force the re-initialization of this

counter/timer when the other counter has an active compare event.

•

0 = External counter/timers can not force a re-initialization of this counter/timer.

•

1 = External counter/timers may force a re-initialization of this counter/timer.

13.9.1.8 Output Mode (OM)—Bits 2–0

These bits determine the mode of operation for the OFLAG output signal.

•

000 = Asserted while counter is active

•

001 = Clear OFLAG output on successful compare

•

010 = Set OFLAG output on successful compare

•

011 = Toggle OFLAG output on successful compare

•

100 = Toggle OFLAG output using alternating compare registers

•

101 = Set on compare, cleared on secondary source input edge

•

110 = Set on compare, cleared on counter rollover

•

111 = Enable Gated Clock output while counter is active2

Note:

Unexpected results may occur if the Output mode field is set to use alternating

Compare registers (mode 100) and the Count Once bit is set.

1. When the Output mode 0

×4 is used, alternating values of CMP1 and CMP2 are used to generate successful compares.

For example, when the Output mode is 0

×4, the counter counts until CMP1 value is reached, reinitializes, then counts

until CMP2 value is reached, reinitializes, then counts until CMP1 value is reached, and so on.

2. Primary count source must be set to one of the counter outputs.

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