DSP56857 datasheet(382/662 Pages) FREESCALE

382 / 662 page

5685X Digital Signal Controller User Manual, Rev. 4

13-16

Freescale Semiconductor

13.9.2.14 Output Polarity Select (OPS)—Bit 1

This bit determines the polarity of the OFLAG Output signal.

•

0 = True polarity

•

1 = Inverted polarity

13.9.2.15 Output Enable (OEN)—Bit 0

When set, this bit enables the OFLAG Output signal to be put on the external pin. Additionally,

setting this bit connects a timer’s output pin to its input. The polarity of the signal will be

determined by the OPS bit.

13.9.3 Timer Channel Compare Register 1 (CMP1)

These read/write registers store the value used for comparison with counter value. There are four

Timer Channel Compare Registers in this occurrence. Their addresses are:

TMRA0_CMP1 (Timer A, Channel 0 Compare 1)—Address:TMRA_BASE + $0

TMRA1_CMP1 (Timer A, Channel 1 Compare 1)—Address: TMRA_BASE + $8

TMRA2_CMP1 (Timer A, Channel 2 Compare 1)—Address:TMRA_BASE + $10

TMRA3_CMP1 (Timer A, Channel 3 Compare 1)—Address: TMRA_BASE + $18

Figure 13-6. TMR Compare Register 1 (CMP1)

See Programmer’s Sheet on Appendix page B - 84

13.9.4 Timer Channel Compare Register 2 (CMP2)

These read/write registers store the value used for comparison with counter value. There are four

Timer Compare Registers in this occurrence. Their addresses are:

TMRA0_CMP2 (Timer A, Channel 0 Compare 2)—Address: TMRA_BASE + $1

TMRA1_CMP2 (Timer A, Channel 1 Compare 2)—Address: TMRA_BASE + $9

TMRA2_CMP2 (Timer A, Channel 2 Compare 2)—Address: TMRA_BASE + $11

TMRA3_CMP2 (Timer A, Channel 3 Compare 2)—Address: TMRA_BASE + $19

Figure 13-7. TMR Compare Register 2 (CMP2)

See Programmer’s Sheet on Appendix page B - 85

Base + $0. $8,

$10, $18

Read

COMPARISON VALUE 1

Write

Reset

0000

000

0000

000

Base + $1, $9,

$11, $19

Read

COMPARISON VALUE 2

Write

Reset

0000

000

0000

000

DSP56857 Datasheet(PDF) 382 Page - Freescale Semiconductor, Inc

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