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DSP56857 Datasheet(PDF) 377 Page - Freescale Semiconductor, Inc |
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DSP56857 Datasheet(HTML) 377 Page - Freescale Semiconductor, Inc |
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377 / 662 page ![]() Register Descriptions (TMR_BASE = $1FFE80) Quad Timer (TMR), Rev. 4 Freescale Semiconductor 13-11 13.9 Register Descriptions (TMR_BASE = $1FFE80) 13.9.1 Timer Control Registers (CTL) There are four Timer Control Registers in this occurrence. Their addresses are: TMRA0_CTRL (Timer A, Channel 0 Control)—Address: TMRA_BASE + $6 TMRA1_CTRL (Timer A, Channel 1 Control)—Address: TMRA_BASE + $E TMRA2_CTRL (Timer A, Channel 2 Control)—Address: TMRA_BASE + $16 TMRA3_CTRL (Timer A, Channel 3 Control)—Address: TMRA_BASE + $1E Figure 13-4. TMR Control Register (CTL) See Programmer’s Sheet on Appendix page B - 90 13.9.1.1 Count Mode (CM)—Bits 15–13 These bits control the basic counting behavior of the counter. • 000 = No operation • 001 = Count rising edges of primary source 1 • 010 = Count rising and falling edges of primary source • 011 = Count rising edges of primary source while secondary input high active1 • 100 = Quadrature count mode, uses primary and secondary sources • 101 = Count rising edges of primary source; secondary source specifies direction (1 = minus) 1 • 110 = Edge of secondary source triggers primary count until compare • 111 = Cascaded Counter mode (up/down)2 13.9.1.2 Primary Count Source (PCS)—Bits 12–9 These bits select the primary count source. • 0000 = Counter 0 input pin (TIO0) • 0001 = Counter 1 input pin (TIO1) • 0010 = Counter 2 input pin (TIO2) Base + $6, $E, $16, $1E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read CM PCS SCS ONCE LENGTH DIR EXT INIT OM (OFLAG) Write Reset 0 0 0 0 000 000 0 0 0 0 0 0 1. Rising edges counted only when IPS = 0. Falling edges counted when IPS = 1. 2. Primary count source must be set to one of the counter outputs. |
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