DSP56857 datasheet(373/662 Pages) FREESCALE

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Counting Modes Definitions

Quad Timer (TMR), Rev. 4

Freescale Semiconductor

13-7

13.7.6 Signed Count Mode

If the Count mode field is set to 101, the counter counts the primary clock source while the

selected secondary source provides the selected count direction (up/down).

13.7.7 Triggered Count Mode

If the Count mode field is set to 110, the counter will begin counting the primary clock source

after a positive transition (Negative Edge if IPS = 1) of the secondary input occurs. The counting

will continue until a compare event occurs, or another positive input transition is detected. If a

second input transition occurs before a terminal count was reached, counting will stop.

Subsequent odd numbered edges of the secondary input will restart counting, while even

numbered edges will stop counting. This will continue until a compare event occurs.

13.7.8 One-Shot Mode

This is a sub mode of triggered event Count mode if the Count mode field is set to 110 while:

•

Count Length (LENGTH) is set

•

OFLAG Output mode is set to 101

•

ONCE bit of the Control (CTRL) register is set to 1

In the above setting, the counter works in a One-Shot mode. An external event causes the counter

to count. When terminal count is reached, the OFLAG output is asserted. This delayed output

assertion can be used to provide timing delays.

13.7.9 Cascade Count Mode

If the Count mode field is set to 111, the counter’s input is connected to the output of another

selected counter. The counter will count up and down as compare events occur in the selected

source counter. This Cascade or Daisy Chained mode enables multiple counters to be cascaded in

order to yield longer counter lengths. When operating in the Cascade mode, a special high speed

signal path is used not using the OFLAG Output signal. If the Selected Source Counter is

counting up, and it experiences a compare event, the counter will be incremented. If the Selected

Source Counter is counting down and it experiences a compare event, the counter will be

decremented. Up to four counters may be cascaded to create a 64-bit wide synchronous counter.

Whenever any counter is read within a Counter module, all of the counters’ values within the

module are captured in their respective Hold Registers. This action supports the reading of a

cascaded counter chain. First read any counter of a cascaded counter chain, then read the Hold

Registers of the other counters in the chain. The Cascaded Counter mode is synchronous.

Note:

It is possible to connect counters together by using the other (non-cascade) Counter

modes and selecting the outputs of other counters as a clock source. In this case, the

DSP56857 Datasheet(PDF) 373 Page - Freescale Semiconductor, Inc