DSP56857 datasheet(371/662 Pages) FREESCALE

371 / 662 page

Counting Modes Definitions

Quad Timer (TMR), Rev. 4

Freescale Semiconductor

13-5

The counter can count the rising, falling, or both edges of the selected input pin. The counter can

decode and count quadrature encoded input signals. The counter can count up and down using

dual inputs in a count with direction format. The counter’s terminal count value (modulo) is

programmable. The value loaded into the counter after reaching its terminal count is

programmable. The counter can count repeatedly, or it can stop after completing one count cycle.

The counter can be programmed to count to a programmed value and then immediately

reinitialize, or it can count through the compare value until the count rolls over to zero.

The external inputs to each counter/timer can be shared among each of the four counter/timers

within the module. The external inputs can be used as:

•

Count commands

•

Timer commands

•

Trigger current counter value to be captured

•

Generate interrupt requests

The polarity of the external inputs can be selected. For this implementation of the Timer (TMR),

there are four input pins. The primary output of each timer/counter is the output signal, OFLAG.

The OFLAG output signal can be set, cleared, or toggled when the counter reaches the

programmed value. The OFLAG output signal may be output to an external pin shared with an

external input signal (TIOx).

The OFLAG output signal enables each counter to generate square waves (PWM) or pulse stream

outputs. The polarity of the OFLAG output signal is selectable.

Any counter/timer can be assigned as a Master (MSTR). A master’s compare signal can be

broadcasted to the other counter/timers within the module. The other counters can be configured

to reinitialize their counters and/or force their OFLAG output signals to predetermined values

when a Master’s Counter/Timer compare event occurs.

13.7 Counting Modes Definitions

The selected external count signals are sampled at the TMR’s base clock rate (60MHz) and then

run through a transition detector. The maximum count rate is one-half of the base peripheral

clock rate. Internal clock sources can be used to clock the counters at the peripheral clock rate.

If a counter is programmed to count to a specific value and then stop, the Count mode in the

TMR_CTRL register is cleared when the count terminates.

13.7.1 Stop Mode

If the Count mode field is set to 000, the counter is inert. No counting will occur.

DSP56857 Datasheet(PDF) 371 Page - Freescale Semiconductor, Inc