DSP56857 datasheet(375/662 Pages) FREESCALE

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Counting Modes Definitions

Quad Timer (TMR), Rev. 4

Freescale Semiconductor

13-9

and the input clock frequency. This method of PWM generation has the advantage of allowing

almost any desired PWM frequency and/or constant on or off periods. This mode of operation is

often used to drive PWM amplifiers used to power motors and inverters.

13.7.13 Compare Registers Use

The dual Compare registers (TMR_CMP1 and TMR_CMP2) provide a bidirectional modulo

count capability. The CMP1 Register is used when the counter is counting up, and the CMP2

operating with alternating compare registers. The CMP1 Register should be set to the desired

maximum count value or $FFFF to indicate the maximum unsigned value prior to roll-over, and

the CMP2 Register should be set to the maximum negative count value or $0000 indicating the

maximum unsigned value prior to roll-under.

If the Output mode is set to 100, the OFLAG will toggle while using alternating Compare

registers. In this Variable Frequency PWM mode, the CMP2 value defines the desired pulse

width of the on-time, and the CMP1 Register defines the off-time. The Variable Frequency PWM

mode is defined for positive counting only.

One must be careful when changing CMP1 and CMP2 while the counter is active. If the counter

has already passed the new value, it will count to $FFFF or $0000, roll over/under, and then

begin counting toward the new value. (The check is for Count = Cmpx, not Count> = Cmp1 or

Count < = Cmp2).

13.7.14 Capture Register Use

The Capture Register stores a copy of the counter’s value when an input edge (positive, negative,

or both) is detected. Once a capture event occurs, no further updating of the Capture Register will

occur until the Input Edge Flag (IEF) is cleared by writing 0 to the IEF.

DSP56857 Datasheet(PDF) 375 Page - Freescale Semiconductor, Inc