DSP56857 datasheet(425/662 Pages) FREESCALE

425 / 662 page

Data Register Access

General Purpose Input/Output (GPIO), Rev. 4

Freescale Semiconductor

15-25

15.8.32 Port H Pull-Up Enable Register (GPIOH_PUER)

Figure 15-41. Port H Pull-Up Enable Register (GPIOH_PUER)

See Programmer’s Sheet on Appendix page B - 136

15.8.32.1 Reserved—Bits 15–3

These bits are reserved or not implemented. They are read as 1 and cannot be modified by

writing.

15.8.32.2 Pull-Up Enable (PUE)—Bits 2–0

This register is not used because pull-ups are always disabled for the MODA, B, and C pins.

15.9 Data Register Access

Care must be taken when accessing the Data Registers. Table 15-10 summarizes the results of

various Data Register accesses in different conditions.

Table 15-10. Data Register Access

Base + $3

Read

PUE

Write

Reset

111

Output

Enable from

Peripheral

PER

DDR

Pad State

Access Type

Data Access Result

Input

Write to DR

Data is written into DR by IPBus. No effect on

the pad value.

Output

Write to DR

Data is written into the DR by the IPBus. DR

value seen at pad.

Input

Read from DR

Pad state is read by the IPBus. No effect on

DR value.

Output

Read from DR

DR value is read by the IPBus. DR value seen

at pad.

Input

Write to DR

Data is written into the DR by the IPBus. No

effect on pad value.

Output

Write to DR

Data is written into the DR by the IPBus.

Peripheral output data is seen at pad.

Input

Read from DR

DR value is read by the IPBus. No effect on

the pad or DR value

Output

Read from DR

DR value is read by the IPBus. Peripheral

output data is seen at the pad.

DSP56857 Datasheet(PDF) 425 Page - Freescale Semiconductor, Inc

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