DSP56857 datasheet(515/662 Pages) FREESCALE

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Sheet

Appendix B - Programmer’s Sheets, Rev. 4

Freescale Semiconductor

B-13

4 of 4

EMI

Bus Control Register (BCR)

Bus Control

$1FFE40 +$18

Bits

Read

DRV

BMDAR

BWWS

BRWS

Write

Reset

0000010

1111

Bits

Name

Description

DRV

Drive

This control bit is used to specify what occurs on the external memory port pins when no external

access is performed. For example, it determines whether pins are placed in tri-state or remain

driven.

14 - 12

BMDAR

Base Minimal Delay After Read

This bit field specifies the number of system clocks to delay after reading from memory not in CS

controlled space. Since a write to the device implies activating the device on the bus, this is also

considered a read from another device, therefore activating the BMDAR timing control. Please see

the description of the MDAR field of the CSTC registers for a discussion of the function of this

control.

9-5

BWWS

Base Write Wait States

This bit field specifies the number of additional system clocks 0-30 (31 is invalid) to delay for write

access to the selected memory when the memory address does not fall within CS controlled range.

The value of BWWS should be set as indicated in Section 5.7.

4-0

BRWS

Base Read Wait States

This bit field specifies the number of additional system clocks 0-30 (31 is invalid) to delay for read

access to the selected memory when the memory address does not fall within CS controlled range.

The value of BRWS should be set as indicated in Section 5.7.

denotes Reserved Bits

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