DSP56857 datasheet(518/662 Pages) FREESCALE

518 / 662 page

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Date:

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Sheet

5685X Digital Signal Controller User Manual, Rev. 4

B-16

Freescale Semiconductor

3 of 4

OCCS

CGM Divide-By

$1FFF10 + $1

Bits

Read

POST

PLLDB

Write

Reset

0000

0111

011

CGM Divide-By Register (CGMCR)

Bits

Name

Description

15 - 13

POST

PLL Post Scaler

The output of the PLL is postscaled by 1-128 based on this field. To change this field, set the SEL

bit to choose the oscillator output, then this field is changed. The SEL bit is then returned to

selecting the PLL postscaled output.

000

PLL output is divided by 1 (default)

001

PLL output is divided by 2

010

PLL output is divided by 4

011

PLL output is divided by 8

100

PLL output is divided by 16

101

PLL output is divided by 32

110

PLL output is divided by 64

111

PLL output is divided by 128

6 - 0

PLLDB

PLL Divide-By

The PLL output frequency is controlled by the PLL divide-by value. Each time a new value is

written into the PLLDB field, the Lock Detector circuit is reset. Before changing the divide-by, set

the SEL bit to choose the oscillator output.

denotes Reserved Bits

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