DSP56857 datasheet(639/662 Pages) FREESCALE

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Sheet

56F853/854/855/857/858 Digital Signal Controller User Manual, Rev. 4

B-137

Freescale Semiconductor

Preliminary

1 of 10

Bits

Name

Description

HRMS

Host Request Mode Select

The Host mode Select (HRMS) bit controls the host request pins

HDDS

Host Dual Data Strobe

When the Host Dual Data Strobe (HDDS) bit is set, the HI8 operates in the Dual Data Strobe

Bus mode; a host bus with separated read and write data strobes. When cleared, the HI8

operates in the Single Strobe Bus mode, i.e. a Host bus with a single Data Strobe signal.

TDMAEN

DSC Side Transmit DMA Enable

The TDMAEN bit is used to enable DSC side Transmit DMA operations. When set, the on-chip

DMA controller handles transferring data between the HTX register and DSC memory. The

on-chip DMA controller must be appropriately configured to implement the desired data transfer.

RDMAEN

DSC Side Receive DMA Enable

The RDMAEN bit is used to enable DSC side Receive DMA operations. When set, the on-chip

DMA controller handles transferring data between the HRX register and DSC memory. The

on-chip DMA controller must be appropriately configured to implement the desired data transfer.

HF2

Host Flags 2 and 3

3HF3

The Host Flag 2 and Host Flag 3 (HF2 and HF3) bits are used as general purpose flags for

DSC-to-Host communication. HF2 and HF3 may be set or cleared by the core. HF2 and HF3

are reflected in the Interrupt Status Register (ISR) on the Host Side if they are modified by the

software, the host processor can read the modified values by reading the ISR.

HCIE

Host Command Interrupt Enable

The HCIE bit is used to enable a core interrupt when the HCP status bit in the HSR is set. When

cleared, HCP interrupts are disabled. When set, a Host Command Interrupt request occurs if

HCP is set. The interrupt address is determined by the Host Command Vector Register. Cleared

on hardware reset.

HTIE

Host Transmit Interrupt Enable

The HTIE bit is used to enable a core interrupt when the Host Transmit Data Empty status bit in

the HSR is set. When cleared, HTDE interrupts are disabled. When set, a Host Transmit Data

Interrupt request occurs when the HTDE bit is set. It is cleared on hardware reset.

HRIE

Host Receive Interrupt Enable

The HRIE bit is used to enable a core interrupt when the Host Receive Data Full (HRDF) status

bit in the Host Status Register (HSR) is set. When cleared, HRDF interrupts are disabled. When

set, a Host Receive Data Interrupt request occurs if the HRDF bit is also set. It is cleared on

hardware reset.

HI8 Host Control

$1FFFD8 + $0

Bits

Read

HRMS HDDS TDMAEN RDMAEN HF3 HF2 HCIE HTIE HRIE

Write

Reset

000

HI8 Host Control Register (HCR)

HI8

denotes Reserved Bits

DSP56857 Datasheet(PDF) 639 Page - Freescale Semiconductor, Inc

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