DSP56857 datasheet(643/662 Pages) FREESCALE

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Sheet

56F853/854/855/857/858 Digital Signal Controller User Manual, Rev. 4

B-141

Freescale Semiconductor

Preliminary

HI8

HI8 Interface Control Register (ICR)

Bits

Name

Description

7INIT

Initialize

The Initialize bit is used by the host processor to force initialization of the HI8 hardware.

HM1

Host Mode Control

5HM0

The Host mode control bits HM0 and HM1 select the Transfer mode of the HI8. HM1 and HM0

enable the DMA mode of operation, or they interrupt a no-Host DMA mode of operation when

HREQ bit in the Host Control Register (HCR) is set.

HF1

Host Flag 1

The Host Flag 1 (HF1) bit is used as a general purpose flag for Host-to-DSC communication.

The HF1 bit can be set or cleared by the host processor, but cannot be changed by the core.

The HF1 bit is cleared on DSC reset.

HF0

Host Flag 0

The Host Flag 0 (HF0) bit is used as a general purpose flag for Host-to-DSC communication.

The HF0 bit can be set or cleared by the host processor, but cannot be changed by the core.

The HF0 bit is cleared on DSC reset.

HLEND

ICR Host Little Endian

This bit allows the HI8 to be accessed by the Host in or Big Endian data order. When the HLEND

bit is set, the HI8 can be accessed by the Host in Little Endian order. The RXH/TXH is located

at address $7 and RXL/TXL at $6. When the HLEND bit is cleared, the HI8 can be accessed by

the Host in Big Endian Host data order. The RXH/TXH is located at address $6 and RXL/TXL

at $7. The HLEND bit is cleared on hardware reset.

TREQ

ICR Transmit Request Enable

This bit is used to control the HREQ pin for Host transmit data transfers. In the Interrupt mode,

and the DMA is off, TREQ is used to enable interrupt requests via the external Host Request

(HREQ or HTRQ) pin when the TXDE status bit in the ISR is set. When TREQ is cleared, TXDE

interrupt is disabled.

RREQ

Receive Request Enable

This bit is used to control the HREQ pin for Host receive data transfers. In the Interrupt mode

(HDMA off), the RREQ is used to enable interrupt requests via the external Host Request

(HREQ or HRRQ) pin when the Receive Data Register Full (RXDF) status bit in the Interrupt

Status register (ISR) is set. When RREQ is cleared, RXDF interrupts are disabled. When RREQ

is set, the external Host Request HREQ pin or HRRQ is asserted if RXDF is set in interrupt

mode.

5 of 10

HI8 Interface

Control Register

(ICR)

$1FFFD8 + $0

Bits

Read

INIT

HM1

HM0

HF1

HF0 HLEND TREQ RREQ

Write

Reset

000

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