DSP56857 datasheet(640/662 Pages) FREESCALE

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Appendix B - Programmer’s Sheets, Rev. 4

Freescale Semiconductor

B-138

Preliminary

2 of 10

HI8

HI8 Status Register (HSR)

Bits

Name

Description

HDMA

Host DMA Status

The Host DMA Status (HDMA) bit indicates the host processor has enabled the Host DMA mode

of the HI8 by setting HM1 or HM0 to 1. When the HDMA status bit is set at 0, it indicates the

Host DMA mode is disabled by the Host mode bits HM0 and HM1, both having been cleared, in

the Interface Control Register ICR and no Host DMA operations are pending. When the HDMA

status bit is set, the Host DMA mode is enabled by the Host mode bits HM0 and HM1. The

transmit or receive channel not in use can be used by the Host for polled or interrupt operation

by the device. HDMA is cleared by a DSC reset.

HF1

Host Flags 0 and 1

3HF0

The Host Flag 0-1 (HF0 and HF1) bits are used as a general purpose flags for Host-to-DSC

communication. The HF0 and HF1 bits can be set or cleared by the Host. These bits reflect the

status of Host Flags HF0 and HF1 in the Interface Control Register (ICR) on the Host Side.

HCP

Host Command Pending

The Host Command Pending (HCP) flag bit reflects the status of the HC bit in the Command

Vector Register (CVR), indicating a Host Command Interrupt is pending. The HCP bit is set

when the HC bit is set, and both bits are cleared by the HI8 hardware when the interrupt request

is serviced by the core. The Host can also clear the HC bit, thereby clearing the HCP bit as well.

The HCP bit is cleared on hardware reset.

HTDE

Host Transmit Data Empty

The Host Transmit Data Empty (HTDE) flag bit indicates the Host Transmit Data (HTX) register

is empty and can be written by the core. The HTDE bit is set when the HTX register is

transferred to the RXH/RXL registers, and cleared when Host Transfer Date (HTX) is written by

the core. When the HTDE bit is set, the HI8 generates a Transmit Data Full DMA request. HTDE

can also be set by the host processor using the initialize function. The HTDE bit is set on

hardware reset.

HRDF

Host Receive Data Full

The Host Receive Data Full (HRDF) flag bit indicates the Host Receive Data (HRX) register

contains data from the host processor. The HRDF bit is set when data is transferred from the

TXH/TXL registers to the Host Receive Data (HRX) register. The HRDF bit is cleared when the

HRX register is read by the core. When the HRDF bit is set, the HI8 generates a receive data

full DMA request. The HRDF bit can also be cleared by the host processor using the initialize

function. The HRDF bit is cleared on hardware reset.

HI8 Host Status

$1FFFD8 + $1

Bits

Read

HDMA HF1

HF0

HCP HTDE HRDF

Write

Reset

000

denotes Reserved Bits

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