DSP56857 datasheet(645/662 Pages) FREESCALE

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Sheet

56F853/854/855/857/858 Digital Signal Controller User Manual, Rev. 4

B-143

Freescale Semiconductor

Preliminary

HI8

HI8 Interface Status Register (ISR)

7 of 10

HI8 Interface

Status Register

(ISR)

$1FFFD8 + $2

Bits

Read

HREQ DMA

HF3

HF2

TRDY TXDE RXDF

Write

Reset

000

Bits

Name

Description

HREQ

Host Request

This bit indicates the status of the external Host Request (HREQ) output pin if the HRMS bit is

cleared; or the external Host Transmit Receive Request (HTRQ) output pins, and HRRQ

respectively, if HRMS is set. When the HREQ status bit is cleared, it indicates the Host Request

pin, HREQ or HTRR, HTRQ and HRRQ, are deasserted and either host processor interrupts or

host DMA transfers are being requested.

DMA

Host DMA Status

The DMA status bit (DMA) indicates that the host processor has enabled the DMA mode of the

HI8 (HM1 or HM0 =1). When the DMA status bit is clear, it indicates that the DMA mode is

disabled by the Host mode bits (HM0 and HM1) in the Interface Control Register ICR and no

DMA operations are pending. When DMA is set, it indicates that the DMA mode is enabled and

the host processor should not use the active DMA channel (RXH:RXL or TXH:TXL depending

on DMA direction) to avoid conflicts with the DMA data transfers.

HF3

Host Flag 3

The Host Flag 3 (HF3) bit in the Interrupt Status Register indicates the state of Host Flag 3 in

the Host Control Register on the DSC side. The HF3 bit can only be changed by the DSC Side.

HF2

Host Flag 2

The Host Flag 2 (HF2) bit in the Interface Control Register (ISR) indicates the state of Host Flag

2 in the Host Control Register on the DSC side. The HF2 bit can only be changed by the DSC

Side.

TRDY

Transmitter Ready

This flag bit indicates TXH, TXL, and the HRX registers are empty. When the TRDY bit is set,

the data the host processor writes to the TXH and TXL registers is immediately transferred to

the DSC side of the HI8. The many applications can use this feature.

TXDE

Transmit Data Register Empty

This bit indicates the transmit byte registers (TXH, and TXL) are empty and can be written by

the host processor. TXDE is set when the transmit byte registers are transferred to the HRX

written by the host processor. TXDE can be set by the host processor using the initialize feature.

RXDF

Receive Data Register Full

This flag bit indicates the receive byte registers (RXH and RXL) contain data from the DSC Side

and can be read by the host processor. The RXDF bit is set when the HTX is transferred to the

receive byte registers. RXDF is cleared when the receive data (RXL or RXH according to

HLEND bit) register is read by the host processor.

denotes Reserved Bits

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