Everest Semiconductor

Confidential

ES7210

Revision 11.1

3

March 2019

2. TYPICAL APPLICATION CIRCUIT

3. CLOCK MODES AND SAMPLING FREQUENCIES

The device supports standard audio clocks (256Fs, 384Fs, 512Fs, etc), USB clocks (12/24 MHz),

and some common non standard audio clocks (25 MHz, 26 MHz, etc).

According to the serial audio data sampling frequency (Fs), the device can work in two speed

modes: single speed mode or double speed mode. In single speed mode, Fs normally ranges

from 8 kHz to 48 kHz, and in double speed mode, Fs normally range from 64 kHz to 96 kHz.

The device can work either in master clock mode or slave clock mode. In slave mode, LRCK and

SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the

system clock with specific rates. In master mode, LRCK and SCLK are derived internally from

device master clock.

4. MICRO-CONTROLLER CONFIGURATION INTERFACE

controller can completely configure the device through writing to internal configuration

registers.

line (CCLK) for data transfer. The timing diagram for data transfer of this interface is given in

Figure 1a and Figure 1b. Data are transmitted synchronously to CCLK clock on the CDATA line on

a byte-by-byte basis. Each bit in a byte is sampled during CCLK high with MSB bit being

transmitted firstly. Each transferred byte is followed by an acknowledge bit from receiver to pull

the CDATA low. The transfer rate of this interface can be up to 400 kbps.

AD0

1

AD1

2

CCLK

4

MCLK

5

VDDD

7

GNDD

8

CDATA

3

VDDP

6

SCLK

9

LRCK

10

SDOUT2/TDMIN

12

INT

13

MIC1N

15

MIC1P

16

SDOUT1/TDMOUT

11

DMIC_CLK

14

MIC2N

20

MICBIAS12

24

MIC2P

19

MICBIAS34

26

MIC4P

28

MIC3P

31

MIC3N

32

MIC4N

27

PGND

33

ES7210

Everest

IIC

IIS

VDDC

VDDP

GPIO

100K

VDDP

100nF

100nF

1uF 1uF 1uF 1uF 1uF

AGND

1uF

VDDA

AGND

1uF

VDDM

AGND

1uF

1uF

1uF

1uF

1uF

AGND

1uF

1uF

1uF

1uF

1uF

AGND

AGND

0R

GND(SYS)

AGND

AGND

Micbias34

Mic4P

Mic4N

Mic3P

Mic3N

Micbias12

Mic2P

Mic2N

Mic1P

Mic1N

*

In the layout, chip is treated as an analog device

* * * *

*

*

*

*

* *

For the best performance,decoupling and filtering capacitors should be located as close to the device package as possible

Additional parallel capacitors(typically 0.1 μF) can be used, larger value capacitors(typically 10 μF) would also help

*