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ES7210 Datasheet(PDF) 9 Page - Suzhou Everest Semiconductor Co. Ltd. |
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ES7210 Datasheet(HTML) 9 Page - Suzhou Everest Semiconductor Co. Ltd. |
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9 / 11 page ![]() Everest Semiconductor Confidential ES7210 Revision 11.1 9 March 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com SERIAL AUDIO PORT SWITCHING SPECIFICATIONS PARAMETER Symbol MIN MAX UNIT MCLK frequency 49.2 MHz MCLK duty cycle 40 60 % LRCK frequency 200 KHz LRCK duty cycle (Note 2) 40 60 % SCLK frequency 26 MHz SCLK pulse width low TSLKL 16 ns SCLK Pulse width high TSCLKH 16 ns SCLK falling to LRCK edge (master mode only) TSLR 10 ns LRCK edge to SCLK rising (slave mode only) TLSR 10 ns SCLK falling to SDOUT valid VDDD=3.3V VDDD=1.8V TSDO 16 39 ns LRCK edge to SDOUT valid (Note 3) VDDD=3.3V VDDD=1.8V T LDO 11 25 ns Note 2: one SCLK period of high time in DSP/PCM modes. Note 3: only apply to MSB of Left Justified or DSP/PCM mode B. Figure 4 Serial Audio Port Timing TSCLKH TLDO TSDO TLSR TSLR TSCLKL SDOUT SCLK LRCK |
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