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TM7708 Datasheet(PDF) 10 Page - Shenzhen Titan Micro Electronics Co., Ltd. |
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TM7708 Datasheet(HTML) 10 Page - Shenzhen Titan Micro Electronics Co., Ltd. |
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10 / 46 page  © Titan Micro Electronics V1.1 www.titanmec.com -10- 24 bit 模数转换器 TM7707/8 为 25Hz 或 50Hz ）。60Hz 时，PSRR 超过 120dB （滤波器陷波为 20Hz 或 60Hz ）。 19. PSRR 由增益和 VDD 决定，如下： 增益 1 2 4 8~128 VDD=3V 86 78 85 93 VDD=5V 90 78 84 91 八、定时参数 （ VDD= +2.7V~+5.2V；GND=0V；fCLKIN =2.4567MHz；Input Logic 0=0 V， Logic 1 = VDD 除非另有说明） Parameter Limit at TMIN ,TMAX (B Version) Units Conditions/Comments fCLKIN 3,4 400 kHzmin Master Clock Frequency: Crystal Oscillator or Externally Supplied 2.5 MHz max for Specified Performance tCLKIN LO 0.4×tCLKIN ns min Master Clock Input Low Time. tCLKIN=1/ fCLKIN tCLKIN HI 0.4×tCLKIN ns min Master Clock Input High Time. t1 500×tCLKIN ns mon DRDY High Time t2 100 ns min RESETPulsewidth Read Operation t3 0 ns min DRDY to CS Setup Time t4 120 ns min CS Falling Edge to SCLK Rising Edge Setup Time t5 5 0 ns min SCLK Falling Edge to Data Valid Delay 80 ns max VDD=+5V 100 ns max VDD=+3.0V t6 100 ns min SCLK High Pulsewidth t7 100 ns min SCLK Low Pulsewidth t8 0 ns min CS Rising Edge to SCLK Rising Edge Hold Time t9 6 10 ns min Bus RelinguishTimeafter SCLK Rising Edge 60 ns max VDD=+5V 100 ns max VDD=+3.0V t10 100 ns max SCLK Falling Edge to DRDY High7 Write Operation t11 120 ns min CS Falling Edge to SCLK Rising Edge Setup Time t12 30 ns min Data Valid to SCLK Rising Edge |
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