GPL191B2

© Generalplus Technology Inc.

Proprietary & Confidential

8

Mar. 08, 2010

Version: 1.1

6.5. LCD Controller/Driver

GPL191B2 contains a 1024-dot LCD driver. Programmers can

set the LCD configuration (bias, duty, voltage doubler) by writing to

LCD control register ($20).

Once the LCD configuration is

initialized, the desired pattern can be displayed by filling the LCD

buffer with appropriate data. The LCD driver can also operate

during sleep by keeping 32768Hz oscillator running. The LCD

driver in GPL191B2 is designed to fit most LCD specifications. It

can either be programmed as 1/4 or 1/5 bias and the duty is also

programmable as 1/8, 1/12, or 1/16 duty.

6.6. Voltage Doubler/Regulator

The GPL191B2 also contains a built-in voltage doubler and a

voltage regulator.

The voltage regulator provides a reference

voltage (HVLCD) for the voltage doubler to generate VLCD (by

charge-pumping). Users can get desired VLCD by changing the

output reference voltage (writing to register) of the voltage

regulator. By enabling the voltage doubler and regulator, users

can get a stable VLCD that will not be affected by VDD. The

three possible configurations of voltage doubler and regulator are

shown in the following table:

Regulator

Doubler

VLCD

OFF

OFF

VDD (not regulated)

OFF

ON

2*VDD (not regulated)

ON

OFF

N/A

ON

ON

Adjustable

Note that when voltage regulator and voltage doubler are enabled,

the p-n junction of I/O’s output PMOS.

6.7. PWM Output

Internally, the GPL191B2 has one PWM output with two sound

channels.

Each channel can be set to play speech or tone

individually. GPL191B2 uses Pulse Width Modulation that could

directly drive speaker or buzzer without any buffer or amplification

circuit.

6.8. Asynchronous Serial Interface (UART)

The

GPL191B2

supports

a

1-channel

UART for

serial

communications.

It supports bit-rate up to 115.2kbps.

UART

operation

is

controlled

by

UART

command

registers.

Configurations such as Tx/Rx interrupt, parity check, parity

even/odd and clock source can be set in command registers.

Two interrupts are generated by Rx and Tx.

The Rx or Tx

interrupt activates when a byte is received or transmitted. By

reading the status register, user knows whether the interrupt is

generated by Rx or Tx. Framing, overrun and parity errors are

detected as each byte is received. All error status can be read

from status register.

The UART supports clock auto calibration.

If this clocking

scheme is selected, standard baud rates from 1.2kbps to

115.2kbps are available. The baud rate is selected by writing to

baud rate control registers. The supported standard baud rates

and their minimum R-oscillator clock frequency required are

shown in the following table:

Baud Rate(bps)

Min. Frosc(Hz)

1200

24000

2400

48000

4800

96000

9600

192000

19200

384000

38400

768000

51200

1024000

57600

1152000

102400

2048000

115200

2304000

If the auto calibration clocking scheme is not selected, users can

get desired baud rates by writing appropriate values to pre-scalar

registers.

Non-standard baud rates can be obtained this way.

When using the non-calibration mode, one should be aware that

the frequency of R-oscillator may alter due to manufacturing

process variations, supply voltage, operating temperature and

tolerance of external R components used.

6.9. Low Voltage Detection

The GPL191B2 provides a 2.6V/2.4V voltage detector to detect a

low voltage event. Users can turn on 2.6V detection and read

bit1 of the port periodically to monitor whether VDD is lower than

2.6V. In addition, if 2.4V detection is turned on and VDD drops

below 2.4V, after a SLEEP command is issued, system will shut

down all activities (LCD bias, LCD display, 32768Hz oscillator) and

enters standby mode to reduce current consumption. This low

voltage power-down can be awakened by a PEF0 key change or

RESET. Users can use this feature to implement the low battery

check/battery change function.

OPERATING

STANDBY

VDD < 2.4V and SLEEP

Port EF0 Key wake-up

or user reset

State Diagram of Low Voltage Power Down