| Electronic Components Datasheet Search |
|
SC4524EEVB Datasheet(PDF) 17 Page - Semtech Corporation |
|
|
|||||||||||||||||||||||||||||
SC4524EEVB Datasheet(HTML) 17 Page - Semtech Corporation |
|
17 / 23 page ![]() SC4524E 7 Applications Information (Cont.) k 10 10 R 3 7 20 = x = − nF 10 10 16 2 1 C 3 3 5 = π = pF 21 10 10 600 2 1 C 3 3 8 = π = k 12.4 10 0.3 R 3 7 20 11.4 = − 10 10 16 2 C 3 3 5 = π pF 10 10 600 2 C 3 3 8 = π x x x x x x x x 12.4 0.8 12.4 Select R 7=2.4k, C5=nF, and C8=22pF for the design. Compensator parameters for various typical applications are listed in Table 5. A MathCAD program is also available upon request for detailed calculation of the compensator parameters. Thermal Considerations For the power transistor inside the SC4524E, the conduction loss P C, the switching loss PSW, and bootstrap circuit loss P BST, can be estimated as follows: O CESAT C I V D P x = SW O IN S SW F I V t 2 1 P = 40 I V D P O BST BST = x x x x x x x whereV BST is the BST supply voltage and tS is the equivalent switching time of the NPN transistor (see Table 4). 1A 2A 12V 12.5ns 15.3ns 24V 22ns 25ns 28V 25.3ns 28ns Load Current Input Voltage In addition, the quiescent current loss is P Q=VINx2mA The total power loss of the SC4524E is therefore P TOTAL=PC+PSW+PBST=PQ The temperature rise of the SC4524E is the product of the total power dissipation (see previous equation) and q JA (36oC/W), which is the thermal impedance from junction to ambient for the SOIC-8 EDP package. It is not recommended to operate the SC4524E above 25oC junction temperature. In the applications with high input voltage and high output current, the switching frequency may need to be reduced to meet the thermal requirement. PCB Layout Considerations In a step-down switching regulator, the input bypass capacitor, the main power switch and the freewheeling diode carry pulse currents (Figure 0). For jitter-free operation,thesizeoftheloopformedbythesecomponents should be minimized. Since the power switch is already integrated within the SC4524E, connecting the anode of the freewheeling diode close to the negative terminal of the input bypass capacitor minimizes size of the switched current loop. The input bypass capacitor should be placed close to the IN pin. Shortening the traces of the SW and BST nodes reduces the parasitic trace inductance at these nodes. This not only reduces EMI but also decreases switching voltage spikes at these nodes. The exposed pad should be soldered to a large ground plane as the ground copper acts as a heat sink for the device. To ensure proper adhesion to the ground plane, avoid using large vias directly under the device. Figure 10 — Pulse current Loop Note: Heavy lines indicate the critical pulse current loop. The stray inductance of this loop should be minimized IN V O UT V L Z Table 4: Typical switching time |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |