LAN91C96ITQFP datasheet(42/110 Pages) SMSC

42 / 110 page

Non-PCI Single-Chip Full Duplex Ethernet Controller

Rev. 11/18/2004

Page 42

SMSC DS – LAN91C96I

DATASHEET

The contents of MIR as well as the low byte of MCR are specified in 256* M bytes. The multiplier M is

determined by bits 11, 10 and 9 as follows:

DEVICE

BIT 11

BIT 10

BIT 9

MAX MEMORY SIZE

FEAST

256 (Note 7.1) 256

(Note 7.1)

2=128k

LAN91C90

256 (Note 7.1) 256

(Note 7.1)

1=64k

FUTURE

256k

FUTURE

512k

FUTURE

Note 7.1 Bits 11, 10 and 9 are read only bits used by the software driver to transparently run on different controllers

of the LAN9000 family.

I/O SPACE - BANK1

OFFSET

NAME

TYPE

SYMBOL

CONFIGURATION REGISTER

READ/WRITE

The Configuration Register holds bits that define the device configuration and are not expected to change

during run-time. This register is part of the EEPROM saved setup in Local Bus mode only.

WAIT

FULL

STEP

SET

SQLCH

AUI

SELECT

16BIT

DIS LINK

Reserved

INT

SEL1

INT

SEL0

function

of EN16*

NO WAIT - When set, does not request additional wait states. An exception to this are accesses to the

Data Register if not ready for a transfer. When clear, negates IOCHRDY for two to three 20MHz clocks on

any cycle to the LAN91C96I.

FULL STEP - This bit is used to select the signaling mode for the AUI port. When set the AUI port uses full

step signaling. Defaults low to half step signaling. This bit is only meaningful when AUI SELECT is high.

SET SQLCH - When set, the squelch level used for the 10BASE-T receive signal is 240mV. When clear

the receive squelch level is 400mV. Defaults low.

AUI SELECT - When set the AUI interface is used, when clear the 10BASE-T interface is used. Defaults

low.

16BIT - Used in conjunction with EN16* and IO is 8 to define the width of the system bus. If the EN16* pin

is low, this bit is forced high. Otherwise the bit defaults low and can be programmed by the host CPU.

DIS LINK - This bit is used to disable the 10BASE-T link test functions. When this bit is high the

LAN91C96I disables link test functions by not generating nor monitoring the network for link pulses. In this

mode the LAN91C96I will transmit packets regardless of the link test, the EPHSR LINK_OK bit will be set

and the LINK LED will stay on. When low the link test functions are enabled. If the link status indicates

FAIL, the EPHSR LINK_OK bit will be low, while transmit packets enqueued will be processed by the

LAN91C96I, transmit data will not be sent out to the cable.

LAN91C96ITQFP Datasheet(PDF) 42 Page - SMSC Corporation

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