GD25B64C datasheet(23/57 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25B64C

Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode

The

Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with

Wrap” (77H) commands prior to EBH. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap

Around” feature for the following EBH commands. When “Wrap Around” is enabled, the data being accessed can be limited

to either an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the

command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning

boundary automatically until CS# is pulled high to terminate the command.

The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the

cache afterwards within a fixed length (8/16/32/64-

byte) of data without issuing multiple read commands. The “Set Burst

with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around”

operation while W6-W5 is used to specify the length of the wrap around section within a page.

7.12.

Quad I/O Word Fast Read (E7H)

The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest

address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure14. The first

byte addressed can be at any location. The address is automatically incremented to the next higher address after each

byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Word

Fast read command.

Quad I/O Word Fast Read with

“Continuous Read Mode”

The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous

Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then

the next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not require the E7H command

code. The command sequence is shown in followed Figure15.

If the “Continuous Read Mode” bits (M5-4) do not equal to (1,

0), the n

ext command requires the first E7H command code, thus returning to normal operation. A “Continuous Read

Mode” Reset command can be used to reset (M5-4) before issuing normal command.

Figure 14. Quad I/O Word Fast Read Sequence Diagram (M5-4

≠ (1, 0))

Command

E7H

CS#

SCLK

IO0

IO1

9 10 11 12 13 14 15

16 17 18 19 20 21 22 23

A23-16 A15-8 A7-0

M7-0

IO2

IO3

Dummy

Byte1 Byte2

Byte3

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