GD25B64CSIG datasheet(39/57 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25B64C

7.33.

Read Security Registers (48H)

The Read Security Registers command is similar to Fast Read command. The command i is followed by a 3-byte

address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content,

at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The

first byte addressed can be at any location. The address is automatically incremented to the next higher address after each

byte of data is shifted out. Once the A9-A0 address reaches the last byte of the register (Byte 3FFH), it will reset to 000H,

the command is completed by driving CS# high.

Address

A23-16

A15-12

A11-10

A9-0

Security Register #1

00H

0 0 0 1

0 0

Byte Address

Security Register #2

00H

0 0 1 0

0 0

Byte Address

Security Register #3

00H

0 0 1 1

0 0

Byte Address

Figure 37. Read Security Registers command Sequence Diagram

7.34.

Enable Reset (66H) and Reset (99H)

If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its

default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch

status (WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Continuous Read Mode bit setting

(M7-M0) and Wrap Bit Setting (W6-W4).

The

“Reset (99H)” command sequence as follow: CS# goes low  Sending Enable Reset command  CS# goes

high  CS# goes low  Sending Reset command  CS# goes high. Once the Reset command is accepted by the device,

the device will take approximately tRST / tRST_E

(30μs/12ms) to reset. During this period, no command will be accepted. Data

corruption may happen if there is an on-going or suspended internal Erase or Program operation when Reset command

sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before

issuing the Reset command sequence.

Command

48H

CS#

SCLK

High-Z

9 10

28 29 30 31

23 22 21

24-bit address

MSB

34 35 36 37

38 39

Data Out1

42 43 44 45

46 47

Data Out2

CS#

SCLK

MSB

Dummy Byte

GD25B64CSIG Datasheet(PDF) 39 Page - GigaDevice Semiconductor (Beijing) Inc.

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