GD25Q127CSJS datasheet(20/79 Pages) GIGADEVICE

20 / 79 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q127C

Hardware Protected Mode is entered.

Figure7. Write Status Register Sequence Diagram

7.6. Read Data Bytes (READ) (03H)

The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), and each bit is latched-in on the

rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max

frequency fR, during the falling edge of SCLK. Then the memory content at that address is shifted out on SO. The first byte

addressed can be at any location. The address is automatically incremented to the next higher address after each byte of

data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) command. Any Read

Data Bytes (READ) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects

on the cycle that is in progress.

Figure8. Read Data Bytes Sequence Diagram

Command

01H/31H/11H

CS#

SCLK

High-Z

9 10 11 12 13 14 15

MSB

Status Register in

Command

03H

CS#

SCLK

High-Z

9 10

28 29 30 31 32

MSB

34 35 36 37

23 22 21

38 39

24-bit address

MSB

Data Out1

Data Out2

GD25Q127CSJS Datasheet(PDF) 20 Page - GigaDevice Semiconductor (Beijing) Inc.