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GD25Q127CSJS Datasheet(PDF) 65 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25Q127CSJS Datasheet(HTML) 65 Page - GigaDevice Semiconductor (Beijing) Inc. |
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65 / 79 page  3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C 65 Figure45. Serial Input Timing Figure46. Output Timing Figure47. Resume to Suspend Timing Diagram Figure48. Hold Timing SCLK CS# SI MSB SO High-Z LSB tCHSL tSLCH tDVCH tCHDX tSHCH tCHSH tCHCL tCLCH tSHSL CS# SCLK SO SI Least significant address bit (LIB) in tCLQV tCLQX tCLQX tCLQV tCLH tCLL tSHQZ LSB CS# SCLK SO HOLD# tCHHL tHLQZ tHLCH tCHHH tHHCH tHHQX SI do not care during HOLD operation. CS# Resume Command tRS Suspend Command |
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