TMS320VC5410A datasheet(13/100 Pages) TI

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2.3

Signal Descriptions

TMS320VC5410A

Fixed-Point Digital Signal Processor

SPRS139G – NOVEMBER 2000 – REVISED JANUARY 2005

Table 2-2 lists each signal, function, and operating mode(s) grouped by function. See Section Section 2.2

for exact pin locations based on package type.

Table 2-2. Signal Descriptions

TERMINAL

I/O(1)

DESCRIPTION

NAME

DATA SIGNALS

A22 (MSB)

I/O/Z(2)(3)

Parallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The sixteen

A21

LSB lines, A0 to A15, are multiplexed to address external memory (program, data) or I/O. The seven MSB

A20

lines, A16 to A22, address external program space memory. A22-A0 is placed in the high-impedance state

A19

in the hold mode. A22-A0 also goes into the high-impedance state when OFF is low.

A18

A16-A0 are inputs in HPI16 mode. These pins can be used to address internal memory via the host-port

A17

interface (HPI) when the HPI16 pin is high. These pins also have Schmitt trigger inputs.

A16

The address bus has a bus holder feature that eliminates passive components and the power dissipation

A15

associated with them. The bus holder keeps the address bus at the previous logic level when the bus goes

A14

into a high-impedance state.

A13

A12

A11

A10

A0 (LSB)

D15 (MSB)

I/O/Z(2)(3)

Parallel data bus D15 (MSB) through D0 (LSB). D15-D0 is multiplexed to transfer data between the core

D14

CPU and external data/program memory or I/O devices or HPI in HPI16 mode (when HPI16 pin is high).

D13

D15-D0 is placed in the high-impedance state when not outputting data or when RS or HOLD is asserted.

D12

D15-D0 also goes into the high-impedance state when OFF is low. These pins also have Schmitt trigger

D11

inputs.

D10

The data bus has a bus holder feature that eliminates passive components and the power dissipation

associated with them. The bus holder keeps the data bus at the previous logic level when the bus goes

into the high-impedance state. The bus holders on the data bus can be enabled/disabled under software

control.

D0 (LSB)

INITIALIZATION, INTERRUPT AND RESET OPERATIONS

Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter is

IACK

O/Z

fetching the interrupt vector location designated by A15-A0. IACK also goes into the high-impedance state

when OFF is low.

INT0 (2)

External user interrupt inputs. INT0-INT3 are maskable and are prioritized by the interrupt mask register

INT1 (2)

(IMR) and the interrupt mode bit. INT0 -INT3 can be polled and reset by way of the interrupt flag register

INT2 (2)

(IFR).

INT3 (2)

Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR.

NMI (2)

When NMI is activated, the processor traps to the appropriate vector location.

Reset. RS causes the digital signal processor (DSP) to terminate execution and forces the program

RS (2)

counter to 0FF80h. When RS is brought to a high level, execution begins at location 0FF80h of program

memory. RS affects various registers and status bits.

(1)

I = Input, O = Output, Z = High-impedance, S = Supply

(2)

These pins have Schmitt trigger inputs.

(3)

This pin has an internal bus holder controlled by way of the BSCR register.

Introduction

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