PIC18F6525T-ESLASHPTSQTP datasheet(97/396 Pages) MICROCHIP

97 / 396 page

 2005 Microchip Technology Inc.

DS39612B-page 95

PIC18F6525/6621/8525/8621

9.3

PIE Registers

The PIE registers contain the individual enable bits for

the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are three Peripheral

Interrupt Enable registers (PIE1, PIE2 and PIE3).

When the IPEN bit (RCON<7>) is ‘0’, the PEIE bit must

be set to enable any of these peripheral interrupts.

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0

PSPIE(1)

ADIE

RC1IE

TX1IE

SSPIE

CCP1IE

TMR2IE

TMR1IE

bit 7

bit 0

bit 7

PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1)

= Enables the PSP read/write interrupt

= Disables the PSP read/write interrupt

Note:

Enabled only in Microcontroller mode for PIC18F8525/8621 devices.

bit 6

ADIE: A/D Converter Interrupt Enable bit

= Enables the A/D interrupt

= Disables the A/D interrupt

bit 5

RC1IE: USART1 Receive Interrupt Enable bit

= Enables the USART1 receive interrupt

= Disables the USART1 receive interrupt

bit 4

TX1IE: USART1 Transmit Interrupt Enable bit

= Enables the USART1 transmit interrupt

= Disables the USART1 transmit interrupt

bit 3

SSPIE: Master Synchronous Serial Port Interrupt Enable bit

= Enables the MSSP interrupt

= Disables the MSSP interrupt

bit 2

CCP1IE: ECCP1 Interrupt Enable bit

= Enables the ECCP1 interrupt

= Disables the ECCP1 interrupt

bit 1

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

= Enables the TMR2 to PR2 match interrupt

= Disables the TMR2 to PR2 match interrupt

bit 0

TMR1IE: TMR1 Overflow Interrupt Enable bit

= Enables the TMR1 overflow interrupt

= Disables the TMR1 overflow interrupt

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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