Data Sheet

ADRF5730

Rev. 0 | Page 7 of 19

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

LE

Latch Enable Input. See the Theory of Operation section for more information.

2

PS

Parallel or Serial Control Interface Selection Input. See the Theory of Operation section for more

information.

3, 4, 6 to 13, 15, 16

GND

Ground. These pins must be connected to the RF and dc ground of the PCB.

5

ATTIN

Attenuator Input. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is

necessary when the RF line potential is equal to 0 V dc.

14

ATTOUT

Attenuator Output. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is

necessary when the RF line potential is equal to 0 V dc.

17

VSS

Negative Supply Input.

18

VDD

Positive Supply Input.

19

D0

Parallel Control Input for 0.5 dB Attenuator Bit. See the Theory of Operation section for more information.

20

D1

Parallel Control Input for 1 dB Attenuator Bit. See the Theory of Operation section for more information.

21

D2

Parallel Control Input for 2 dB Attenuator Bit. See the Theory of Operation section for more information.

22

D3/SEROUT

Parallel Control Input for 4 dB Attenuator Bit (D3).

Serial Data Output (SEROUT). See the Theory of Operation section for more information.

23

D4/SERIN

Parallel Control Input for 8 dB Attenuator Bit (D4).

Serial Data Input (SERIN). See the Theory of Operation section for more information.

24

D5/CLK

Parallel Control Input for 16 dB Attenuator Bit (D5).

Serial Clock Input (CLK). See the Theory of Operation section for more information.

EPAD

Exposed Pad. The exposed pad must be connected to the RF and dc ground of the PCB.

INTERFACE SCHEMATICS

Figure 5. Digital Input Interface (LE, PS, D3/SEROUT, D4/SERIN, D5/CLK)

Figure 6. ATTIN and ATTOUT Interface

Figure 7. Digital Input Interface (D0, D1, D2)

PS

LE

GND

GND

ATTIN

GND

VSS

VDD

GND

GND

ATTOUT

GND

10

18

13

17

16

15

14

11

12

7

8

9

21

20

19

24

23

22

1

6

2

3

4

5

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED

TO THE RF AND DC GROUND OF THE PCB.

ADRF5730

TOP VIEW

(Not to Scale)

VDD

VDD

LE, PS, D3/SEROUT,

D4/SERIN, D5/CLK

ATTIN,

ATTOUT

VDD

VDD

100kΩ

D0, D1, D2