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CY28317-2
Document #: 38-07094 Rev. *B
Page 19 of 21
Layout Diagram
G = VIA to GND plane layer
V = VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors
FB
+3.3V Supply
C4
Ceramic Caps C3 = 10–22
µF C4 = 0.005 µF
10
µF
FB = Dale ILB1206 - 300 (300
Ω @ 100 MHz) or TDK ACB2012L-120
0.005
µF
G
G
VDDQ3
C3
C6 = 0.01
µF
48
47
46
45
44
43
42
41
40
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
39
G
V
G
V
G
V
G
V
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
V
G
G
G
FB
+2.5V Supply
C4
10
µF
0.005
µF
G
G
VDDQ2
C3
G
V
G
V
G