Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

LTC5555 Datasheet(PDF) 13 Page - Analog Devices

Part # LTC5555
Description  1.5GHz to 7GHz Programmable Gain Downconverting Mixer
PDF  26 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LTC5555 Datasheet(HTML) 13 Page - Analog Devices

Back Button LTC5555 Datasheet HTML 9Page - Analog Devices LTC5555 Datasheet HTML 10Page - Analog Devices LTC5555 Datasheet HTML 11Page - Analog Devices LTC5555 Datasheet HTML 12Page - Analog Devices LTC5555 Datasheet HTML 13Page - Analog Devices LTC5555 Datasheet HTML 14Page - Analog Devices LTC5555 Datasheet HTML 15Page - Analog Devices LTC5555 Datasheet HTML 16Page - Analog Devices LTC5555 Datasheet HTML 17Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 13 / 26 page
background image
LTC5555
13
Rev. 0
For more information www.analog.com
PIN FUNCTIONS
GND (Pins 1, 8, 14, 15, 16 Exposed Pad Pin 29): Ground.
These pins must be soldered to the RF ground plane on
the circuit board. The exposed pad provides both electri-
cal ground contact and thermal contact to the printed
circuit board.
AI–,AI+(Pins2,3):DifferentialIFAttenuatorInputs.These
pins are internally biased to VCC/2 when VCC is applied.
Therefore, a series DC-blocking capacitor must be used.
EN (Pin 4): Enable Control Pin. A CMOS logic high will
enable the IC. This pin has an internal 330k pull-down
resistor, so if unconnected, the IC will be disabled.
VCC(Pin5):PowerSupplyPin.Thispinmustbeconnected
to a regulated 3.3V supply with a bypass capacitor located
close to the pin. Typical DC current consumption is 41mA.
The Supply voltage on this pin defines the logic levels for
the EN and PS pins.
MO+, MO– (Pins 6, 7): Mixer Open-Collector Differential
IF Outputs. These pins must be connected to VCC through
pull-up inductors or transformer windings. Typical DC
current is 27mA into each pin.
RF (Pin 9): Single-Ended RF Input. This pin is internally
biased to VCC/2 when VCC is applied. Therefore, a series
DC-blocking capacitor must be used.
CSB (Pin 10): Serial Port Chip Select and Parallel Data
Latch. In serial control mode this CMOS input allows serial
port communication when driven low and ends the burst
when taken back high. In parallel mode, a rising edge on
this pin loads the parallel data on pins 17 – 21 into the
internal data latch. See the Applications Information sec-
tion for more details.
CLK (Pin 11): Serial Port Clock. This CMOS input clocks
serial port input data on its rising edge. See the Applica-
tions Information section for more details. This pin is
inactive when PS is high.
SDI (Pin 12): Serial Port Data Input. This CMOS input
is used to load serial data into the 8-bit register. See Ap-
plications Information section for more details. This pin
is inactive when PS is high.
SDO (Pin 13): Serial Port Data Output. This CMOS tri-state
output presents data from the serial port during a read
communicationburst.Optionally,attacharesistorof>200k
to GND to prevent a floating output. See the Applications
Information section for more details. This pin is inactive
when PS is high.
D4, D3, D2, D1, D0 (Pins 17 – 21): Parallel Control Pins
for Gain. These CMOS inputs control the IF DVGA gain
when the CSB pin transitions from low to high. The gain
may also be controlled through the serial port when PS is
low. For serial only control, it is recommended that these
pins be grounded.
PS (Pin 22): Parallel Select Pin. A CMOS logic high will
enable IF DVGA control using the parallel data pins (pins
17 – 21). A CMOS logic low allows the SPI port to control
the gain while ignoring the voltages on the parallel data
pins. This pin has an internal 330k pull-down resistor.
RP (Pin 23): Reduced Power Select Pin. A CMOS logic
low on this pin sets the IC to full power mode, unless
programmed to reduced power mode by the SPI. A CMOS
logic high programs the IC to reduced power mode,
independent of the SPI. This pin has an internal 330k
pull-down resistor.
LO–, LO+ (Pins 24, 25): Differential Local Oscillator Input.
These pins are internally connected to ESD diodes to
ground. Therefore, series DC-blocking capacitors must be
used if the LO source has a DC voltage present. Single-
ended or differential drive may be used. Each pin is inter-
nally matched to 50Ω, even when the mixer is disabled.
VDD (Pin 26): Power Supply Pin for SPI and Parallel Inter-
face Logic. This pin must be connected to a regulated 1.8V
to 3.3V supply. Typical DC current consumption is less
than 1mA with CSB low and the clock running at 10MHz.
Whenidle,typicalcurrentconsumptionislessthan500μA.
The Supply voltage on this pin defines the logic levels for
the SPI I/O pins (CSB, CLK, SDI, and SDO), the parallel
data pins (D0 − D4) and the RP pin.
IF–, IF+ (Pins 27, 28): Open Collector Differential IF Buf-
fer Output. These pins must be connected to VCC through
pull-up inductors. Typical DC current is 48mA per pin.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com