LTC5555 datasheet(21/26 Pages) AD

21 / 26 page

LTC5555

Rev. 0

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APPLICATIONS INFORMATION

SPI PROGRAMMING

Data transfers to the part are accomplished by first tak-

ing CSB low to enable the port. Then, serial input data

on SDI is captured on the rising edge of CLK and shifted

into an 8-bit shift register, MSB first. Serial data from

the registers is driven out to SDO on the clock’s falling

edge. The communication burst is terminated by taking

CSB high. The rising edge on CSB will then latch the

shift-register’s contents into an 8-bit buffer D-latch. The

buffer latch prevents the downconverter’s gain and power

mode from changing while data is loaded. See Figure 15

for timing details.

When CSB is high, the clock and data inputs are internally

gated off, minimizing current consumption when not se-

lected, and the SDO output is high impedance. However,

it is recommended that the serial interface signals should

remain idle between data transfers to avoid digital noise

coupling into the RF signal paths.

AmemorymapoftheregistercontentsisshowninTable7,

with detailed bit descriptions in Table 8. Each bit’s default

power-up value is also shown in Table 8, which is:

• 0dB IF attenuation (maximum gain)

• Full power mode

Figure 14. SPI Block Diagram

Figure 15. SPI Timing Diagram

5555 F15

CLK

SDI

tENABLE

tDELAY

tRISE,FALL

tHOLD

tDISABLE

tHOLD(CSB)

tSETUP

tSETUP(CSB)

SDO

CSB

SDI

CLK

CSB

(LSB)

VDD

(MSB)

SDO

SPI LATCH

POR

• • •

5555 F14

PARALLEL LATCH

D[7:0]

D[4:0]

D4 D3 D2 D1 D0

D[7:0]

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