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AT73C213 Datasheet(PDF) 13 Page - ATMEL Corporation |
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AT73C213 Datasheet(HTML) 13 Page - ATMEL Corporation |
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13 / 35 page ![]() 13 2744A–PMGMT–27-Jan- AT73C213 2744A–PMGMT–27-Jan-05 8.3 SPI Interface Timing Figure 8-2. SPI Timing Thsdi Tssen Tc Twl Twh Thsen Tssdi SPI_DOUT SPI_DIN SPI_CLK Tdsdo Thsdo SPI_CSB Table 8-1. SPI Timing Parameters Parameter Description Min Max Tc SPI_CLK min period 100 ns - Twl SPI_CLK min pulse width low 50 ns - Twh SPI_CLK min pulse width high 50 ns - Tssen Setup time SPI_CSB falling to SPI_CLK rising 50 ns - Thsen Hold time SPI_CLK falling to SPI_CSB rising 50 ns - Tssdi Setup time SPI_DIN valid to SPI_CLK falling 20 ns - Thsdi Hold time SPI_CLK falling to SPI_DIN not valid 20 ns - Tdsdo Delay time SPI_CLK rising to SPI_DOUT valid - 20 ns Thsdo Hold time SPI_CLK rising to SPI_DOUT not valid 0 ns - |
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