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UPD3728DZ Datasheet(PDF) 8 Page - NEC |
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UPD3728DZ Datasheet(HTML) 8 Page - NEC |
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8 / 28 page  Data Sheet S15417EJ2V0DS 8 µµµµPD3728DZ TIMING CHART 2 (Bit clamp mode, for each color) Symbol Min. Typ. Max. Unit t1, t2 0 50 − ns t1’, t2’ 05 − ns t3 17 50 − ns t4 5 200 − ns t5, t6 0 20 − ns t7 17 150 − ns t8, t9 0 20 − ns t10 −10 Note 1 +50 − ns t11 −5 Note 2 +50 − ns tcp 5 150 − ns Notes 1. Min. of t10 shows that the φ RB and φ CLB overlap each other. 2. Min. of t11 shows that the φ 1L and φ CLB overlap each other. RB CLB 90% 90% t10 φ φ 1L CLB 90% 90% t11 φ φ 90% t10 t1' t5 t6 t4 t3 t2' td VOS RFTN 10% t11 t9 t8 tcp t7 t1 t2 90% 10% 90% 10% 10% 90% 10% 90% 10% VOUT1 to VOUT6 RB φ CLB φ 10) φ 1 ( φ 1L φ 20) φ 2 ( φ |
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