3.5

Commands

Refresh Mode

SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS -before-RAS

refresh of conventional DRAMs. All banks must be precharged before applying any refresh mode. An on-chip

address counter increments the word and the bank addresses and no bank information is required for both

refresh modes.

clock timing. The mode restores word line after the refresh and no external precharge command is necessary. A

minimum tRC time is required between two automatic refreshes in a burst refresh mode. The same rule applies to

any access command after the automatic refresh operation.

The chip has an on-chip timer and the Self Refresh mode is available. The mode restores the word lines after,

RAS CAS

and CKE are low and WE is high at a clock timing. All of external control signals including the clock

are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit

command, at least one tRC delay is required prior to any access command.

Auto Precharge

Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS timing accepts one

extra address, CA10, to determine whether the chip restores or not after the operation. If CA10 is high when a

Read Command is issued, the Read with Auto-Precharge function is initiated. If CA10 is high when a Write

Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the

precharge operation a time delay equal to tWR (“write recovery time”) after the last data in. A burst operation with

Auto-Precharge may only be interrupted by a burst start to another bank. It must not be interrupted by a

precharge or a burst stop command.

Precharge Command

timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are used to define banks as

shown in the following list. The precharge command can be imposed one clock before the last data out for CAS

latency = 2 and two clocks before the last data out for CAS latency = 3. Writes require a time delay tWR (“write

recovery time”) of 2 clocks minimum from the last data out to apply the precharge command.

T

able 7

Bank Selection by Address Bits

A10

BA0

BA1

0

0

0

Bank 0

0

0

1

Bank 1

0

1

0

Bank 2

0

1

1

Bank 3

1

X

X

All Banks

Burst Termination

Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst

operation prematurely. These methods include using another Read or Write Command to interrupt an existing

burst operation, use a Precharge Command to interrupt a burst cycle and close the active bank, or using the

Burst Stop Command to terminate the existing burst operation but leave the bank open for future Read or Write

Commands to the same page of the active bank. When interrupting a burst with another Read or Write Command

care must be taken to avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions

making it the easiest method to use when terminating a burst operation before it has been completed. If a Burst

Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be

ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the

memory.

AS4C16M32SC-7TIN

AS4C32M16SC-7TIN

AS4C64M8SC-7TIN

Confidential

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Rev.1.0 Sep. 2018