STM32L4A6XG datasheet(49/282 Pages) STMICROELECTRONICS

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DS11584 Rev 8

49/282

STM32L4A6xG

Functional overview

3.28

HASH hardware accelerator (HASH)

The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-

1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and the

HMAC (keyed-hash message authentication code) algorithm suitable for a variety of

applications.

It computes a message digest (160 bits for the SHA-1 algorithm, 256 bits for the SHA-256

algorithm and 224 bits for the SHA-224 algorithm,128 bits for the MD5 algorithm) for

messages of up to (264 - 1) bits, while HMAC algorithms provide a way of authenticating

messages by means of hash functions. HMAC algorithms consist in calling the SHA-1,

SHA-224, SHA-256 or MD5 hash function twice.

3.29

Timers and watchdogs

The STM32L4A6xG includes two advanced control timers, up to nine general-purpose

timers, two basic timers, two low-power timers, two watchdog timers and a SysTick timer.

The table below compares the features of the advanced control, general purpose and basic

timers.

3.29.1

Advanced-control timer (TIM1, TIM8)

The advanced-control timer can each be seen as a three-phase PWM multiplexed on 6

channels. They have complementary PWM outputs with programmable inserted dead-

Table 10. Timer feature comparison

Timer type

Timer

Counter

resolution

Counter

type

Prescaler

factor

DMA

request

generation

Capture/

compare

channels

Complementary

outputs

Advanced

control

TIM1, TIM8

16-bit

Up, down,

Up/down

Any integer

between 1

and 65536

Yes

General-

purpose

TIM2, TIM5

32-bit

Up, down,

Up/down

Any integer

between 1

and 65536

Yes

General-

purpose

TIM3, TIM4

16-bit

Up, down,

Up/down

Any integer

between 1

and 65536

Yes

General-

purpose

TIM15

16-bit

Any integer

between 1

and 65536

Yes

General-

purpose

TIM16, TIM17

16-bit

Any integer

between 1

and 65536

Yes

Basic

TIM6, TIM7

16-bit

Any integer

between 1

and 65536

Yes

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