68HC05JB3 datasheet(18/134 Pages) FREESCALE

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GENERAL RELEASE SPECIFICATION

November 5, 1998

MOTOROLA

GENERAL DESCRIPTION

MC68HC05JB3

1-6

REV 1

External Clock

An external clock from another CMOS-compatible device can be connected to the

OSC1 input, with the OSC2 input not connected, as shown in Figure 1-3(b).This

conﬁguration is possible ONLY when the crystal/ceramic resonator mask option is

selected.

1.4.3 RESET

This is an I/O pin. This pin can be used as an input to reset the MCU to a known

start-up state by pulling it to the low state. The RESET pin contains a steering

diode to discharge any voltage on the pin to VDD, when the power is removed. An

internal pull-up is also connected between this pin and VDD. The RESET pin con-

tains an internal Schmitt trigger to improve its noise immunity as an input. This pin

is an output pin if LVR triggers an internal reset.

1.4.4 IRQ

This input pin drives the asynchronous IRQ interrupt function of the CPU. The IRQ

interrupt function has a mask option to provide either only negative edge-sensitive

triggering or both negative edge-sensitive and low level-sensitive triggering. If the

option is selected to include level-sensitive triggering, the IRQ input requires an

external resistor to VDD for "wired-OR" operation, if desired. The IRQ pin contains

an internal Schmitt trigger as part of its input to improve noise immunity.

NOTE

Each of the PA0 to PA3 I/O pins may be connected as an OR function with the IRQ

interrupt function by a mask option. This capability allows keyboard scan

applications where the transitions or levels on the I/O pins will behave the same

as the IRQ pin. The edge or level sensitivity selected by a separate mask option

for the IRQ pin also applies to the I/O pins OR’ed to create the IRQ signal.

1.4.5 3.3V

This is an output reference voltage nominally set at 3.3V dc.

1.4.6 D+ and D–

These two lines carry the USB differential data. For low speed device such as

MC68HC05JB3, a 1.5 k

Ω resistor is required to be connected across D– and 3.3V

for proper signal termination.

1.4.7 PA0-PA7

These eight I/O lines comprise Port A. PA0 to PA7 are push-pull pins with pull-

down devices. The state of any pin is software programmable and all Port A lines

are conﬁgured as inputs during power-on or reset.

Freescale Semiconductor, Inc.

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