LPC47M14X datasheet(157/205 Pages) SMSC

157 / 205 page

SMSC DS – LPC47M14X

Page 157

Rev. 03/19/2001

ADDRESS

DESCRIPTION

STATE

Chip Level, SMSC Defined

Device ID -

Hard wired

Default = 0x5F

on VCC POR,

VTR POR,

SOFT RESET and

HARD RESET

0x20 R

A read only register which provides device

identification. Bits[7:0] = 0x5F when read.

Device Rev

Hard wired

= Current Revision

0x21 R

A read only register which provides device revision

information. Bits[7:0] = current revision when read.

PowerControl

Default = 0x00

on VCC POR,

VTR POR,

SOFT RESET and

HARD RESET

0x22 R/W

Bit[0] FDC Power

Bit[1] Reserved

Bit[2] Game Port Power

Bit[3] Parallel Port Power

Bit[4] Serial Port 1 Power

Bit[5] Serial Port 2 Power (Note 1)

Bit[6] Serial Port 3 Power

Bit[7] Reserved

0: Power Off or Disabled

1: Power On or Enabled

Power Mgmt

Default = 0x00

on VCC POR,

VTR POR and

HARD RESET

0x23 R/W

Bit[0] FDC (see Note in the “FDC Power

Management” section.)

Bit[1] Reserved

Bit[2] Reserved

Bit[3] Parallel Port

Bit[4] Serial Port 1

Bit[5] Serial Port 2

Bit[6] Serial Port 3

Bit[7] Reserved (read as 0)

For each bit above (except Reserved)

= 0

Intelligent Pwr Mgmt off

= 1

Intelligent Pwr Mgmt on

OSC

Default = 0x44, on

VCC POR,

VTR POR and

HARD RESET

0x24 R/W

Bit[0] Reserved

Bit [1] PLL Control

= 0

PLL is on (backward Compatible)

= 1

PLL is off

Bits[3:2] OSC

= 01

Osc is on, BRG clock is on.

= 10

Same as above (01) case.

= 00

Osc is on, BRG Clock Enabled.

= 11

Osc is off, BRG clock is disabled.

Bit [5:4] Reserved, set to zero

Bit [6] 16-Bit Address Qualification

= 0

12-Bit Address Qualification

= 1

16-Bit Address Qualification

Note: For normal operation, bit 6 should be set.

Bit[7] Reserved

LPC47M14X Datasheet(PDF) 157 Page - SMSC Corporation

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