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LPC47M14X Datasheet(PDF) 161 Page - SMSC Corporation

Part # LPC47M14X
Description  128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB
PDF  205 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

LPC47M14X Datasheet(HTML) 161 Page - SMSC Corporation

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SMSC DS – LPC47M14X
Page 161
Rev. 03/19/2001
Table 65 – I/O Base Address Configuration Register Description
LOGICAL
DEVICE
NUMBER
LOGICAL
DEVICE
REGISTER
INDEX
BASE I/O
RANGE
(NOTE 1)
FIXED
BASE OFFSETS
0x00
FDC
0x60,0x61
[0x0100:0x0FF8]
ON 8 BYTE BOUNDARIES
+0 : SRA
+1 : SRB
+2 : DOR
+3 : TSR
+4 : MSR/DSR
+5 : FIFO
+7 : DIR/CCR
0x01
Reserved
n/a
n/a
n/a
0x02
Reserved
n/a
n/a
n/a
[0x0100:0x0FFC]
ON 4 BYTE BOUNDARIES
(EPP Not supported)
or
[0x0100:0x0FF8]
ON 8 BYTE BOUNDARIES
+0 : Data/ecpAfifo
+1 : Status
+2 : Control
+400h : cfifo/ecpDfifo/tfifo/cnfgA
+401h : cnfgB
+402h : ecr
0x03
Parallel
Port
0x60,0x61
(all modes supported,
EPP is only available when
the base address is on an 8-
byte boundary)
+3 : EPP Address
+4 : EPP Data 0
+5 : EPP Data 1
+6 : EPP Data 2
+7 : EPP Data 3
0x04
Serial Port 1
0x60,0x61
[0x0100:0x0FF8]
ON 8 BYTE BOUNDARIES
+0 : RB/TB/LSB div
+1 : IER/MSB div
+2 : IIR/FCR
+3 : LCR
+4 : MSR
+5 : LSR
+6 : MSR
+7 : SCR
0x05
Serial Port 2
0x60,0x61
[0x0100:0x0FF8]
ON 8 BYTE BOUNDARIES
+0 : RB/TB/LSB div
+1 : IER/MSB div
+2 : IIR/FCR
+3 : LCR
+4 : MSR
+5 : LSR
+6 : MSR
+7 : SCR
0x06
Reserved
n/a
n/a
n/a
0x07
KYBD
n/a
Not Relocatable
Fixed Base Address: 60,64
+0 : Data Register
+4 : Command/Status Reg.
0x08
Reserved
n/a
n/a
n/a
0x09
Game Port
0x60,0x61
[0x0100:0x0FFF]
on 1 byte boundaries
+00: Game Port Register
0x0A
Runtime
Register
Block
0x60,0x61
[0x0000:0x0F7F]
on 128-byte boundaries
+00 : PME Status
.
.
.
+5F : Keyboard Scan Code
(See Table in “Runtime Registers”
section for Full List)



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