PRELIMINARY

Rev. 3.0

- 6 -

July 2004

PRELIMINARY

K6R1004V1D

CMOS SRAM

for AT&T

Address

Data Out

Previous Valid Data

Valid Data

TIMING DIAGRAMS

WRITE CYCLE*

* The above parameters are also guaranteed at industrial temperature range.

Parameter

Symbol

K6R1004V1D-08

K6R1004V1D-10

Unit

Min

Max

Min

Max

Write Cycle Time

8-

10

-

ns

Chip Select to End of Write

6-7-

ns

Address Set-up Time

0-0-

ns

Address Valid to End of Write

6-7-

ns

Write Pulse Width(OE High)

6-7-

ns

Write Pulse Width(OE Low)

8-

10

-

ns

Write Recovery Time

0-0-

ns

Write to Output High-Z

04

05

ns

Data to Write Time Overlap

4-5-

ns

Data Hold from Write Time

0-0-

ns

End of Write to Output Low-Z

3-3-

ns

Valid Data

High-Z

CS

Address

OE

Data out

50%

50%

Current