PRELIMINARY

Rev. 3.0

- 7 -

July 2004

PRELIMINARY

K6R1004V1D

CMOS SRAM

for AT&T

NOTES(READ CYCLE)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

device.

5. Transition is measured

±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

Address

CS

Valid Data

WE

Data in

Data out

High-Z(8)

High-Z

OE

Address

CS

Valid Data

WE

Data in

Data out

(10)

(9)

High-Z(8)

High-Z