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ST92195D Datasheet(PDF) 117 Page - STMicroelectronics |
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ST92195D Datasheet(HTML) 117 Page - STMicroelectronics |
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117 / 249 page  117/249 ST92195C/D - ON SCREEN DISPLAY (OSD) ON SCREEN DISPLAY (Cont’d) 7.4.6.3 Building a Serial Mode, 40-Char, Line Mode Display Half-Page Location The 0.5 Kbyte block of half-page content is stored in the TDSRAM location pointed to by the PG3..PG0 bits. Header & Status Rows Location The 0.5 Kbyte block containing the Header, Status Row 0 and Status Row 1 is pointed to by the HS3..HS0 bits. The Row attribute (row count) is stored in this block at offset 100h and contains 12 bytes for line mode (see DCM1R register descrip- tion). Row Scrolling Buffer Location The scrolling buffer corresponds to Row 12 when the scrolling feature is used (in this case 11 rows are scrolled). Figure 73. Serial (40 Characters) Line Mode Mapping 0.5K TDSRAM Row 1 Row 11 Row 12/ Scrolling Buffer Free Space Resolution 0.5K bytes See Figure 70 on page 115 for Address Values 0.5K TDSRAM Header Char. Resolution 0.5K bytes Status Row 0 Status Row 1 Free Space Row Attr. Free Space 100h Block Number (0.5K) TDSRAM Address (hex.) TDPR Value (Hex.) PG3..PG0 0 8000 0 1 8200 1 2 8400 2 3 8600 3 4 8800 4 5 8A00 5 6 8C00 6 7 8E00 7 8 9000 8 9 9200 9 10 9400 A 11 9600 B 12 9800 C 13 9A00 D 14 9C00 E 15 9E00 F 6K 2K 8K |
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