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ST92195D Datasheet(PDF) 144 Page - STMicroelectronics |
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ST92195D Datasheet(HTML) 144 Page - STMicroelectronics |
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144 / 249 page  144/249 ST92195C/D - SYNC CONTROLLER SYNC CONTROLLER (Cont’d) 7.5.5 Register Description SYNC CONTROLLER CONTROL AND STATUS REGISTER 0 (SCCS0R) R242 - Read/Write Register Page: 35 Reset value: 0000 0000 (00h) Bit 7= VPOL. VSYNC Polarity When MOD[1:0] are reset, this bit configures the polarity of the VSYNC input. 0: Negative polarity (leading edge is falling edge) 1: Positive polarity (leading edge is rising edge) For other cases: Bit 6= HPOL. HSYNC/CSYNC Polarity. 0: Negative polarity (leading edge is falling edge) 1: Positive polarity (leading edge is rising edge) Bit 5= VSEP. Separate Sync This bit selects either HSYNC/VSYNC or CSYNC synchro controller mode. It is only valid when MOD[1:0] are reset: 0: The standard mode using two inputs (VSYNC and HSYNC) is activated. 1: The Composite Sync mode is activated; the CSYNC input (on the same pin as HSYNC) will be used to get both H and V signals. For other cases: Bit 4= VDLY. Vertical Delay control bit. This bit is active only if the Composite Sync mode is enabled. The selection of this bit can effect noise margin (longer delay is better) and the field detection. 0: Vertical is generated after detecting a pulse greater than 16µs 1: Vertical is generated after detecting a pulse greater than 32µs Bits 3:0= HSF. Horizontal Shift for Field detection. These 4 bits program the delay, in steps of 4µs (50Hz) or 2µs (100Hz), applied to the HSYNC pulse in order to properly determine the field infor- mation by comparison with VSYNC. This value is a chassis constant depending upon the way the sep- arate H/V signals are generated. 0 VPOL HPOL VSEP VDLY HSF3 HSF2 HSF1 HSF0 MOD1 MOD0 VPOL 0 0 x VSYNC polarity control x 1 0 interlaced x 1 1 non-interlaced 1 x 0 interlaced 1 x 1 non-interlaced MOD1 MOD0 VSEP CSO alternate function 0 0 x disabled x 1 0 disabled x 1 1 enabled 1 x 0 disabled 1 x 1 enabled |
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