ST92195D datasheet(154/249 Pages) STMICROELECTRONICS

154 / 249 page

154/249

ST92195C/D - TELETEXT SLICER AND ACQUISITION UNIT

TELETEXT SLICER AND ACQUISITION UNIT (Cont’d)

7.7.4.2 Data Storage

The data issued by the filtering unit is then sent to

the data storage area, which forwards these bytes

to the TDSRAM controller for storing in TDSRAM

memory. As the TDSRAM interface is synchro-

nized with the chassis sync signals, not necessar-

ily in phase with the CVBS signal, a data stack is

implemented in the data storage area. This data

stack is called the “Acquisition Buffer”.

The Acquisition Buffer is tailored to stack on a TV

line base, all the Teletext data that may come

while no RAM storage is possible. This leads to a 3

byte buffer (for more details, refer to the TDSRAM

Interface Specification).

The data bytes issued by the data filtering unit are

stored into the Acquisition Buffer only if they

passed successfully the different checks (ex-

plained in the preceding chapters; i.e. if the “Write

Enable” flag received from the filtering unit is set).

If the “Write Enable” flag is “0” then the current

byte will be rejected (not written into the Acquisi-

tion Buffer).

Acquisition Buffer Management

After being written to by the filtering unit, the Ac-

quisition Buffer is read by the TDSRAM interface

to transfer data to the internal TDSRAM. As the

two accesses are not “in phase”, the Acquisition

Buffer is built as a FIFO controlled by two pointers:

write and read. Each time a data transfer to the

TDSRAM interface is performed, a control line

called “ACQWEN” will tell the TDSRAM interface if

a write to the TDSRAM must be performed.

The ACQWEN line is set each time data is availa-

ble in the buffer (read and write pointers compari-

son). This allows a TDSRAM write. If the buffer is

empty read and write pointers comparison), the

ACQWEN line is reset and no TDSRAM write is al-

lowed. The TDSRAM interface will perform a read

operation to the TDSRAM; for more details, refer

to the TDSRAM interface specification.

7.7.4.3 Address Generation

The address generation unit provides to the

TDSRAM interface the real time address where

the byte must be stored into the internal TDSRAM.

The address is generated on a 14 bits word length,

allowing to access the TDSRAM memory as a

contiguous space of up to 16 K-bytes.

The TDSRAM memory Address, referred as “AD-

DREG”, is software programmable through 2 reg-

isters ACQAD1R, ACQAD0R (refer to the regis-

ters description for more details).

The ADDREG must be initialized by software. Af-

terwards during each VBI, it will be incremented

each time a byte is stored in the corresponding

memory area. The ADDREG follows a post-incre-

ment scheme, i.e. it is always pointing to the next

free byte location.

A second register, called the "Backup Address"

packet (under reception) address's first byte.

HCVBS (Horizontal Sync Pulse) could be detected

before the end of the TV line Teletext data is re-

ceived because a sync pulse arrived during the

time when Teletext data was sliced, so the TV line

looks too short. The Backup Address value is re-

loaded into the ADDREG, providing the erasure of

the already stored data of the "too short" TV line.

At the same time, the read and write pointers of

the Buffer are re-initialized to the first Buffer loca-

tion (empty Buffer status).

Note: A TV line which is longer than 41 bytes is

considered

"too

long".

Only

the

first

bytes of data are stored. The next acquisition stor-

age starts after a valid Framing code detection.

Warning: Accessing the ADDREG Registers dur-

ing the Vertical Blank Interval when the Teletext

Acquisition is running may lead to a malfunctioning

of the TDSRAM interface addressing.

ST92195D Datasheet(PDF) 154 Page - STMicroelectronics

ST92195D Datasheet(HTML) 154 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL