ST92195D datasheet(193/249 Pages) STMICROELECTRONICS

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ST92195C/D - TWO-CHANNEL I2C BUS INTERFACE (I2C)

I2C BUS INTERFACE (Cont’d)

Bit 1 = UNEXP

Unexpected flag bit

This bit is useful for error detection in a multimas-

ter mode system, when a master is continuing its

transaction while an other concurrent master

wants to finish or restart a transaction by sending a

“Start” or a “Stop” condition.

Together with the MISP bit, it covers all possible

cases, where unexpected “Start” or “Stop” condi-

tions occur, while the interface is a master.

0: No Unexpected error detected

1: A master interface receives a “Start” or a “Stop”

condition, while sending the first bit of a data

byte.

Notes:

– If this bit is set, it will automatically activate the

ERROR bit.

– This bit is only valid when the Advanced Fea-

tures Enable bit AFEN is set.

Bit 0 = MISP

Misplaced flag bit

This bit indicates if the interface has received a

misplaced “Start” or “Stop” condition during ad-

dress transfer or any data byte transfer (besides

first data bit). This error detection is also activated

during the acknowledge bit transfer.

Together with the UNEXP bit, it covers all possible

cases, where unexpected “Start” or “Stop” condi-

tions occur, while the interface is a master.

0: No misplaced “start” or “stop” condition has

been detected

1: A misplaced “Start” or “Stop” condition has been

received.

Note: If this bit is set, it will automatically activate

the ERROR bit.

STATUS REGISTER 1 (I2CSTR1)

R245 - Read Only

Reset Value: 0000 0000(00h)

Bit 7 = ERROR

ERROR detection bit

This bit indicates if an error occurred on the bus or

not.

0: No error detected

1: An error is detected. It is an illegal start or stop

condition, i.e. a signal level transition occurs on

the SDA bus during presence of a clock pulse

on the SCL bus.

An interrupt is generated in this case. The inter-

face stays in the error state until the error flag is

reset by either a CLEAR operation, a STOP re-

quest or a “Return To Inactive State” operation.

Note: the ERROR bit has higher priority than the

ARB_LOST bit (i.e. when ERROR=1, the value of

ARB_LOST has to be ignored).

ERROR

ARB_

LOST

READ FIRST

GEN_

CALL

ACK_

BIT

ACT_

SLV

ACTIVE

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