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SC16C752IB48 Datasheet(PDF) 29 Page - NXP Semiconductors |
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SC16C752IB48 Datasheet(HTML) 29 Page - NXP Semiconductors |
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29 / 47 page  Philips Semiconductors SC16C752 Dual UART with 64-byte FIFO Product data Rev. 04 — 20 June 2003 29 of 47 9397 750 11635 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 7.14 FIFO ready register The FIFO ready register provides real-time status of the transmit and receive FIFOs of both channels. The FIFO Rdy register is a read-only register that can be accessed when any of the two UARTs is selected CSA or CSB = 0, MCR[2] (FIFO Rdy Enable) is a logic 1, and loop-back is disabled. The address is 111. Table 22: FIFO Ready Register bits description Bit Symbol Description 7-6 FIFO Rdy[7:6] Unused; always 0. 5 FIFO Rdy[5] RX FIFO B status. Related to DMA. 4 FIFO Rdy[4] RX FIFO A status. Related to DMA. 3-2 FIFO Rdy[3:2] Unused; always 0. 1 FIFO Rdy[1] TX FIFO B status. Related to DMA. 0 FIFO Rdy[0] TX FIFO A status. Related to DMA. |
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