Input

Logic

Output

Bus-Hold Latch

21

SN74AXCH2T45

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SCES881 – FEBRUARY 2020

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8.4 Bus-Hold Data Inputs

Each data input on this device includes a weak latch that maintains a valid logic level on the input. The state of

these latches is unknown at startup and remains unknown until the input has been forced to a valid high or low

state. After data has been sent through a channel, the latch then maintains the previous state on the input if the

line is left floating. It is not recommended to use pull-up or pull-down resistors together with a bus-hold input, as

it may cause undefined inputs to occur which leads to excessive current consumption.

Bus-hold data inputs prevent floating inputs on this device. The Implications of Slow or Floating CMOS Inputs

application report explains the problems associated with leaving CMOS inputs floating.

These latches remain active at all times, independent of all control signals such as direction control or output

enable.

The Bus-Hold Circuit application report has additional details regarding bus-hold inputs.

Figure 6. Simplified Schematic For Device With Bus-Hold Data Inputs

8.5 Device Functional Modes

(1)

Input circuits of the data I/Os are always active.

Table 2. Function Table

CONTROL INPUT

Port Status

OPERATION

DIR

A PORT

B PORT

L

Output (Enabled)

Input (Hi-Z)

B data to A bus

H

Input (Hi-Z)

Output (Enabled)

A data to B bus