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RM0016 Datasheet(PDF) 86 Page - STMicroelectronics |
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RM0016 Datasheet(HTML) 86 Page - STMicroelectronics |
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86 / 467 page  Clock control (CLK) RM0016 86/467 DocID14587 Rev 14 Figure 23. Clock switching flowchart (manual mode example) 9.3 Low-speed clock selection The Low-speed clock source for the AWU or the independent watchdog can be LSI or HSE divided according to the CKAWUSEL option bit. Refer to option bytes section in the datasheet. The division factor for HSE has to be programmed in the HSEPRSC[1:0] option bits Refer to in the option bytes section of the datasheet. The goal is to get 128 kHz at the output of the HSE prescaler. 9.4 CPU clock-divider The CPU clock (fCPU) is derived from the master clock (fMASTER), divided by a factor programmed in the CPUDIV[2:0] bits in the Clock divider register (CLK_CKDIVR). Seven division factors (1 to 128 in steps of power of 2) can be selected (refer to Figure 20). The fCPU signal is the clock for both the CPU and the window watchdog. |
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