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97SD3232 Datasheet(PDF) 14 Page - Maxwell Technologies

Part # 97SD3232
Description  1 Gb SDRAM 8-Meg X 32 Bit X 4-Banks
PDF  39 Pages
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Manufacturer  MAXWELL [Maxwell Technologies]
Direct Link  http://www.maxwell.com
Logo MAXWELL - Maxwell Technologies

97SD3232 Datasheet(HTML) 14 Page - Maxwell Technologies

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97SD3232
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All data sheets are subject to change without notice
©2005 Maxwell Technologies
All rights reserved.
1 Gb (8-Meg X 32-Bit X 4-Banks) SDRAM
01.11.05 Rev 2
From PRECHARGE state, command operation
To [DESL], [NOP]: When these commands are executed, the SDRAM enters the IDLE state after t
RP has
elapsed from the completion of precharge.
From IDLE state, command operation
To [DESL], [NOP], [PRE], or [PALL]: These commands result in no operation.
To [ACTV]: The bank specified by the address pins and the ROW address is activated.
To [REF], [SELF]: The SDRAM enters refresh mode (auto-refresh or self-refresh).
To [MRS]: The synchronous DRAM enters the mode register set cycle.
From ROW ACTIVE state, command operation
To [DESL], [NOP]: These commands result in no operation.
To [READ], [READ A]: A read operation starts. (However, an interval of t
RCD is required.)
To [WRIT], [WRIT A]: A write operation starts. (However, an interval of t
RCD is required.)
Write with auto-
precharge
H
x
x
x
x
DESL
Continue burst to end and pre-
charge
L
H
H
H
x
NOP
Continue burst to end and pre-
charge
L
H
L
H
BA, CA, A10
READ/READ A
ILLEGAL1
L
H
L
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL1
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank4
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL1
L
L
L
H
x
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
Refresh ( auto-
refresh)
H
x
x
x
x
DESL
Enter IDLE after t
RC
L
H
H
H
x
NOP
Enter IDLE after t
RC
L
H
L
H
BA, CA, A10
READ/READ A
ILLEGAL3
L
H
L
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL3
L
L
H
H
BA, RA
ACTV
ILLEGAL3
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL3
L
L
L
H
x
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
1. Illegal for same bank, except for another bank
2. NOP for same bank, except for another bank
3. Illegal for all banks
4. If t
RRD is not satisfied, this operation is illegal
5. An interval of t
DPL is required between the final valid data input and the precharge command
CURRENT STATE
CS
RAS
CAS
WE
ADDRESS
COMMAND
OPERATION



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